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04/2011 ara2000 address-programmable reverse amplifer with step attenuator data sheet - rev 2.3 fea tures ? low cost integrated amplifer with step attenuator ? attenuation range: 0-58 db, adjustable in 1db increments via a 3 wire serial control ? meets docsis distortion requirements at a +60dbmv output signal level ? programmable address allows multiple parts to share control bus ? low distortion and low noise ? frequency range: 5-100mhz ? 5 volt operation ? -40 to +85 o c temperature range applica tions ? mcns/docsis compliant cable modems ? catv interactive set-top box ? telephony over cable systems ? opencable set-top box ? residential gateway the ara2000 is designed to provide the reverse path amplifcation and output level control functions in a catv set-top box or cable modem. it incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifer stage, and followed by an ultra-linear output driver amplifer. this device uses a balanced circuit design that exceeds the mcns/docsis requirement for harmonic performance at a +60dbmv output level while only requiring a single polarity +5v supply. both the input and output are matched to 75 ohms with an appropriate transformer. the precision attenuator provides up to 58 db of attenuation in 1 db increments. the ara2000 has a programmable address that allows multiple devices to share a common control bus. the ara2000 is offered in a 28-pin ssop package featuring a heat slug on the bottom of the package. product description figure 1: cable modem or set t op box application diagram s12 package 28 pin ssop with heat slug
2 data sheet - rev 2.3 04/2011 ara2000 figure 2: functional block diagram figure 3: pin out
data sheet - rev 2.3 04/2011 3 ara2000 t able 1: pin description notes: (1) all n/c pins should be grounded. (2) pins should be ac-coupled. no external dc bias should be applied. pin name description pin name description 1 gnd ground 15 c0 device address 0 2 v attn supply for attenuator 16 c1 device address 1 3 att in (+) attenuator (+) input (2) 17 n/c no connection (1) 4 a1 out (+) amplifier a1 (+) output 18 gnd cmos ground for digital cmos circuit 5 a1 in (+) amplifier a1 (+) input (2) 19 att out (-) attenuator (-) output (2) 6 vg1 amplifier a1 (+/-) control 20 a2 in (-) amplifier a2 (-) input (2) 7 i set1 amplifier a1 (+/-) current adjust 21 a2 out (-) amplifier a2 (-) output 8 a1 in (-) amplifier a1 (-) input (2) 22 i set2 amplifier a2 (+/-) current adjust 9 a1 out (-) amplifier a1 (-) output 23 vg2 amplifier a2 (+/-) control 10 att in (-) attenuator (-) input (2) 24 a2 out (+) amplifier a2 (+) output 11 v cmos supply for digital cmos circuit 25 a2 in (+) amplifier a2 (+) input (2) 12 clk clock 26 att out (+) attenuator (+) output (2) 13 dat data 27 n/c no connection (1) 14 en enable 28 gnd ground
4 data sheet - rev 2.3 04/2011 ara2000 electrica l characteristics t able 2: absolute minimum and maximum ratings t able 3 : operating ranges s tresses in excess of the absolute ratings may cause permanent damage. f unctional operation is not implied under these conditions. e xposure to absolute ratings for extended periods of time may adversely affect reliability. t he device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defned in the electrical specifcations. notes: 1. pins 3, 5, 8, 10, 19, 20, 25 and 26 should be ac-coupled. no external dc bias should be applied. 2. pins 7 and 22 should be grounded or pulled to ground through a resistor. no external dc bias should be applied. parameter min max unit analog supply (pins 2, 4, 9, 21, 24) 0 9 vdc digital supply: v cmos (pin 11) 0 vdc amplifier controls vg1, vg2 (pins 6, 23) -5 2 v rf power at inputs (pins 5, 8) +60 dbmv digital interface (pins 12, 13, 14, 15, 16) -0.5 v cmos +0.5 v storage temperature -55 +200 ? c soldering temperature 260 ? c soldering time 5 sec parameter min typ max unit amplifier supply: v (pins 4, 9,21,24) 4.5 5.0 7.0 vdc attenuator supply: v attn (pin 2) v -0.5 5.0 7.0 vdc digital supply: v cmos (pin 11) 3.0 5.5 vdc digital interface (pins 12, 13, 14, 15,16) 0 v cmos v amplifier controls vg1, vg2 (pins 6, 23) -5 1 2 v case temperature -40 25 85 ? c
data sheet - rev 2.3 04/2011 5 ara2000 note: as measured in anadigics test fxture t able 4 : dc electrical specifcations t a =25 c; v dd , v a ttn , v cmos = +5.0 vdc; vg1, vg2 = +1.0 v (t x enabled); vg1, vg2 = 0 v (t x disabled) t able 5 : ac electrical specifcations t a =25 c; v dd , v a ttn , v cmos = +5.0 vdc; vg1, vg2 = +1.0 v (t x enabled); vg1, vg2 = 0 v (t x disabled) parameter min typ max unit comments gain (10 mhz) 27.5 29.3 30.5 db 0 db attenuation setting gain flatness 0.75 1.5 db 5 to 42 mhz 5 to 65 mhz gain variation over temperature -0.006 db/ 8 c attenuation steps 1 db 2 db 4 db 8 db 16 db 32 db 0.65 1.6 3.6 7.5 15.0 30.2 0.83 1.70 3.75 7.75 15.40 30.75 1.00 2.05 4.0 8.0 15.8 31.3 db monotonic maximum attenuation 58.6 60.3 db 2 nd harmonic distortion level (10 mhz) -75 -53 dbc +60 dbmv into 75 ohms 3 harmonic distortion level (10 mhz) -60 -53 dbc +60 dbmv into 75 ohms 3 order output intercept 78 dbmv 1 db gain compression point 68.5 dbmv noise figure 3.0 4.0 db includes input balun loss parameter min typ max unit comments amplifier a1 current (pins 4, 9) 48 2.4 80 tx enabled tx disabled amplifier a2 current (pins 21, 24) 77 3.7 120 9 tx enabled tx disabled attenuator current (pin 2) 9 15 total power consumption 0.67 75 1.08 150 tx enabled tx disabled thermal resistance ( j jc 38 4 c/w
6 data sheet - rev 2.3 04/2011 ara2000 continued : ac electrical specifcations a =25 c; v dd , v a ttn , v cmos = +5.0 vdc; vg1, vg2 = +1.0 v (t x enabled); vg1, vg2 = 0 v (t x disabled) note: as measured in anadigics test fxture parameter min typ max unit comments output noise power active/ no signal/ min. atten. set active/ no signal/ max. atten. set. - - - - -38.5 -53.8 dbmv any 160 khz bandwidth from 5 to 42 mhz isolation (45 mhz) in tx disable mode - 65 - db difference in output signal between tx enable and tx disable differential input impedance - 300 - ohms between pins 5 and 8 (tx enabled) input impedance - 75 - ohms with transformer (tx enabled) input return loss (75 ohm characteristic impedance) - - -20 -5 -12 - db tx enabled tx disabled differentail output impedance - 300 - ohms between pins 21 and 24 output impedance - 75 - ohms with transformer output return loss (75 ohm characteristic impedance) - - -17 -15 -12 -10 db tx enabled tx disabled output voltage transient tx enable/ tx disable - - - 4 100 7 mvp-p 0 db attenuator setting 24 db attenuator setting
data sheet - rev 2.3 04/2011 7 ara2000 figure 4: t est circuit
8 data sheet - rev 2.3 04/2011 ara2000 f igure 5: attenuation level vs c ontrol word figure 6: gain & noise figure vs frequency performance da t a figure 7: gain & noise figure vs v dd
data sheet - rev 2.3 04/2011 9 ara2000 figure 8: gain & noise figure vs t emperature figure 9: harmonic distortion vs v dd p out = 58dbmv figure 10: harmonic distortion vs v dd p out = 58dbmv
10 data sheet - rev 2.3 04/2011 ara2000 f igure 11: harmonic distortion vs t emperature p out = 58dbmv figure 12: harmonic distortion vs power out figure 13: t ransients vs attenuation p out = 55dbmv at 0db attenuation
data sheet - rev 2.3 04/2011 11 ara2000 figure 14: harmonic performance over frequency p out = +62dbmv figure 15: iip 2 & iip 3 vs frequency figure 16: iip 2 & iip 3 vs v dd
12 data sheet - rev 2.3 04/2011 ara2000 t able 6: p rogramming word logic programming t able 7: data description t able 8: d evice address programming instructions the programming word is set through a 16 bit shift register via the data, clock and enable lines. the data is entered in order with the most signifcant bit (msb) frst and the least signifcant bit (lsb) last. the enable line must be low for the duration of the data entry, then set high to latch the shift register. the rising edge of the clock pulse shifts each data value into the register. the device is selected when the logic inputs at pins 16 and 15 match the values of data bits c1 and c0, respectively. d ata b it d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 value p7 p6 p5 p4 p3 p2 p1 p0 0 0 0 1 c1 c0 1 1 value function ( 1 = on, 0 = bypass) p7 n/a p6 n/a p5 32 db attenuator bit p4 16 db attenuator bit p3 8 db attenuator bit p2 4 db attenuator bit p1 2 db attenuator bit p0 1 db attenuator bit logic level input to address device c1 c0 pin 16 (c1) pin 15 (c0) 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1
data sheet - rev 2.3 04/2011 13 ara2000 figure 17: serial data input t iming table 9: digital interface specifcation parameter min typ max unit logic high input: v h 2.0 - - v logic low input: v l - - 0.8 v logic input current consumption - - 0.01 ma data to clock set up time: t cs 50 - - ns data to clock hold time: t ch 10 - - ns clock pulse width high: t cwh 50 - - ns clock pulse width low: t cwl 50 - - ns clock to load enable setup time: t es 50 - - ns load enable pulse width: t ew 50 - - ns rise time: t r - 10 - ns fall time: t f - 10 - ns t cs t ch t cwl t cwh t es t ew da t a clock enable or enable d 15 : msb d 14 d 8 d 7 d 1 d 0 : lsb
14 data sheet - rev 2.3 04/2011 ara2000 data sheet - rev 2.3 03/2011 applica tion informa tion t ransmit enable / disable the ara2000 includes two amplifcation stages that each can be shut down through external control pins vg1 and vg2 (pins 6 and 23, respectively.) by applying a slightly positive bias of typically +1.0 volts, the amplifer is enabled. in order to disable the amplifer, the control pin needs to be pulled to ground. a practical way to implement the necessary control is to use bias resistor networks similar to those shown in the test circuit schematic (figure 4.) each network includes a resistor shunted to ground that serves as a pull-down to disable the amplifer when no control voltage is applied. when a positive voltage is applied, the network acts as a voltage divider that presents the required +1.0 volts to enable the amplifer. by selecting different resistor values for the voltage divider, the network can accommodate different control voltage inputs. the vg1 and vg2 pins may be connected together directly, and controlled through a single resistor network from a common control voltage. amplifer bias current the i s e t pins (7 and 22) set the bias current for the amplifcation stages. grounding these pins results in the maximum possible current. by placing a resistor from the pin to ground, the current can be reduced. the recommended bias conditions use the confguration shown in the test circuit schematic in figure 4. thermal layout considerations the device package for the ara2000 features a heat slug on the bottom of the package body. use of the heat slug is an integral part of the device design. soldering this slug to the ground plane of the pc board will ensure the lowest possible thermal resistance for the device, and will result in the longest mtf (mean time to failure.) a pc board layout that optimizes the benefts of the heat slug is shown in figure 18. the via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide a suffcient heat sink. the recommended solder mask outline is shown in figure 19. figure 18: pc board layout
data sheet - rev 2.3 04/2011 15 ara2000 figure 19: solder mask outline output t ransformer matching the output of the ara2000 to a 75 ohm load is accomplished using a 2:1 turns ratio transformer. in addition to providing an impedance transformation, this transformer provides the bias to the output amplifer stage via the center tap. the transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifers. as a result, care must be taken when selecting the transformer to be used at the output. it must be capable of handling the rf and dc power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. it also must operate over the desired frequency and temperature range for the intended application. esd sensitivity electrostatic discharges can cause permanent damage to this device. electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. proper precautions and handling are strongly recommended. refer to the anadigics application note on esd precautions.
16 data sheet - rev 2.3 04/2011 ara2000 figure 20: s12 package outline - 28 pin ssop with heat slug p ackage outline
data sheet - rev 2.3 04/2011 17 ara2000 component p ackaging figure 22: t ape dimensions volume quantities of the ara2000 are supplied on tape and reel. each reel holds 3,500 pieces. figure 21: reel dimensions
18 data sheet - rev 2.3 04/2011 ara2000 notes
data sheet - rev 2.3 04/2011 19 ara2000 notes
20 data sheet - rev 2.3 04/2011 ara2000 notes
war ning anadigics products are not intended for use in life support appliances, devices or systems. use of an anadigics product in any such application without written consent is prohibited. import ant notice anadigics, inc. 141 mount bethel road warren, new jersey 07059, u.s.a. tel: +1 (908) 668-5000 fax: +1 (908) 668-5132 url: http://www.anadigics.com e-mail: mktg@anadigics.com anadigics, inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. the product specifcations contained in advanced product information sheets and preliminary data sheets are subject to change prior to a products formal introduction. information in data sheets have been carefully checked and are assumed to be reliable; however, anadigics assumes no responsibilities for inaccuracies. anadigics strongly urges customers to verify that the information they are using is current before placing orders. data sheet - rev 2.3 04/2011 21 ara2000 ordering informa tion order number temperature range package description component packaging ara2000s12p1 -40 to 85 c 28 pin ssop with heat slug 3,500 piece tape and reel

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